1. Field of Invention
The present invention relates to a display driving apparatus, and more particularly, to a display driving apparatus applicable for driving a liquid crystal display panel and a multi-scan line inversion driving method thereof.
2. Description of Related Art
Thin film transistor liquid crystal displays (TFT LCDs) have become one of the main streams of flat panel displays (FPDs), and source drivers are among the major power consumption for TFT LCD driving apparatuses.
At present, large panels are generally driven by dot inversion, and the largest power consumption thereof is related to the polarity inversion frequency of the scan lines, wherein the greater the frequency is, the more power will be consumed. FIG. 1A is a polarity view of sub-pixels driven by dot inversion according to a conventional art. Referring to FIG. 1A, each grid represents a sub-pixel, and the symbol in the grid represents the polarity of the sub-pixel when driven (+ represents a positive polarity drive, − represents a negative polarity drive), wherein the sub-pixel driving polarities of two adjacent scan lines are opposite (for example, the polarities of scan line S1 and scan line S2 are opposite). During the period that two scan lines are turned on sequentially, the polarity of each of the data lines D1˜D8 must be switched between positive and negative polarities. Every time when a polarity inversion is performed, it represents that each of the data lines D1˜D8 has a larger voltage swing, so the source driver needs more power to implement dot inversion. In other words, the faster the polarity inversion frequency of the sub-pixels in the data lines D1˜D8 is, the more power the source driver consumes.
FIG. 1B is a timing view of single-line inversion driving signals according to the conventional art. Referring to FIG. 1B, each positive half-period +POL or negative half-period −POL of a line polarity signal POL corresponds to a pulse signal of a gate clock signal GCLK, a latch delay signal of a source data latch signal LD and an enabling signal pulse of a gate enabling signal GES. The negative edge of the source data latch signal LD represents the time for the source driver to start outputting a sub-pixel driving signal. The time length of the gate enabling signal GES being at a low level represents the turn-on time length of the corresponding scan line. Therefore, the longer the gate enabling signal GES is at a low level, or the shorter the delay time of the source data latch signal LD is, the longer the sub-pixels of the corresponding scan line is charged. The line polarity signal POL is inverted every time after a scan line is turned on, i.e., the polarity of the data lines D1˜D8 must be switched between positive and negative polarities in the period when any two adjacent scan lines are turned on. As such, the power consumption of the source driver becomes greater.
Of course, the gate enabling signal GES can also adopt a time length of high level to represent the turn-on time length of the corresponding scan lines. Referring to FIG. 1C, the longer the gate enabling signal GES is at a high level, or the shorter the delay time of the source data latch signal LD is, the longer the sub-pixels of the corresponding scan line is charged. Similarly, according to the timing of the line polarity POL, the higher polarity inversion frequency for the data lines D1˜D8 during the period when any two adjacent scan lines are turned on, the more power the source driver consumes.
With the coming of a high pixel era, in order to maintain the frame quality, a higher polarity inversion frequency for sub-pixels is needed, which may cause greater power consumption.